Address
Form of workJob Responsibilities
• Lead and manage ASIC CAD organization and drive towards Best in class ASIC CAD methodologies
• Develop and Drive common FE methodologies across SoC /IP Design and Verification.
• Be an expert in the FE domain Design and Verification Methodologies and collaborate with the execution team for deployment
• Provide leadership to the Design and Verification community for the FE CAD domain.
• Develop, enhance, and integrate ASIC Design and Verification Methodologies and Flows and deploy them for global use.
• Drive Innovative solutions to improve Quality, Efficiency, Planning and Tracking of ASIC methodologies and processes.
• Work with Dedication compute team, prioritize and drive efficient usage of compute server and multi-clusters.
• Work with EDA vendors to adopt the Latest technologies and most optimal solutions for silicon verification and design.
• Work with all stake-holders and align on successful deployment / transition on flows
Job Qualifications:
• Ba
...Job Responsibilities
• Lead and manage ASIC CAD organization and drive towards Best in class ASIC CAD methodologies
• Develop and Drive common FE methodologies across SoC /IP Design and Verification.
• Be an expert in the FE domain Design and Verification Methodologies and collaborate with the execution team for deployment
• Provide leadership to the Design and Verification community for the FE CAD domain.
• Develop, enhance, and integrate ASIC Design and Verification Methodologies and Flows and deploy them for global use.
• Drive Innovative solutions to improve Quality, Efficiency, Planning and Tracking of ASIC methodologies and processes.
• Work with Dedication compute team, prioritize and drive efficient usage of compute server and multi-clusters.
• Work with EDA vendors to adopt the Latest technologies and most optimal solutions for silicon verification and design.
• Work with all stake-holders and align on successful deployment / transition on flows
Job Qualifications:
• Bachelors/Masters in Engineering with Overall CAD domain experience of 12+ years
• Minimum 5+ years of experience in people management with experienced Team members
• Well-rounded and familiar with most Front-End Tools, Flows and Methodologies.
• Experienced writing scripts/software with industry standard languages such as Python, TCL, Perl, C/C++ or SystemC.
• Experience using industry standard HVLs like SystemVerilog, UVM.
• Expertise in the following areas: GIT Management, CI/CD flows, Regression Management, Dashboard planning and Tracking, License management.
• Expertise in standard Audit process / flows and implementation of Flows / checklists for High standard Process adherence
• Broad experience in : Logic design, Design Verification, Design for Test (DFT), Validation, Emulation and FPGA design, Design Integration, Design and Verification IP Libraries, Gate Level Simulation, Verilog Generators, and Low Power design.
• Preferred experience in AI/ML flows and implementation
• Strong Leadership and communication skills and drive towards Innovative solutions
