AddressJob Description
Experience with owning the full chip/Block level and taping out multiple complex
SoCs.Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc.
Full-Chip/Block Level Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc.
RTL to gds2 flow and basic device physics.
Scripting with tcl, perl, shell etc. to solve the basic design problem.
Internal flow development and understand nuances of Physical Design (Structural Design) flow.
Experience with 7nm technology or below.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: The candidate must have a Bachelor's degree in Computer/Electrical Engineering or Computer Science and 4+ years of experience -OR- a Master's Degree in Computer/Electrical Engineering or Computer Science and 2+ years of experience -OR- a PhD in Computer/Electrical Engineering or Computer Science and 1+ year of experience with the following: Experience with owning the full chip level and taping out multiple complex SoCs Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc. Must have good understanding on all or some of Full-Chip Level Partitioning, Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, understanding and hand-on experience of digital design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc. In-depth understanding on rtl to gds2 flow and understanding of basic device physics. The candidate should have the minimum proficiency with basic scripting with tcl, perl, shell etc. to solve the basic design problem Past experience with internal flow development and understand nuances of Physical Design (Structural Design) flow. Working experience with cutting edge technology (7nm or below) Preferred Qualifications: Experience with handling developing PDKs (Process Design Kit) Strong scripting proficiency in PERL, tcl Good handle on Tape-out interaction with the foundry and worked on Post-Silicon activities Exposure to various industry standard Physical Design and Sign-Off closure tools Understanding of peer domains to Physical Design, viz., RTL, verification, DFx, post-Si etc. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Inside this Business Group
Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
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Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
JobType
Hybrid
