AddressJob Description
Performs lowlevel and complex debug for multiple systems, subsystems within a product, or at the SoC level for Intel products. Works to continuously improve the debug discipline through new design for debug (DFD) tools and scripts. Applies deep understanding of SoC design, architecture, firmware, and software to resolve triage failures, marginality issues, and conduct root cause analysis. Defines, develops, and implements techniques for faster debug at the SoC and platform level and isolates failing components of a system. Drives bench test and formulates debug requirements and strategies at the system level, ensuring compatibility with architecture. Develops test methodologies for new device features and functionality, engages in new product debug, and improves debugging workflow and characterization activities. Collaborates with design, system validation teams, and high volume manufacturing factories to track SoC debug readiness.
Qualifications
Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years of experience - OR - Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience - OR - PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field experience in:
- CMOS circuit design, and layout verification
- Industry standard CAD tools/flows for digital and/or analog design
Preferred Qualifications: Experience in:
- Fusion Compiler/Primetime Process and Design co-optimization for Density/Performance improvements RTL based power estimation and optimization
- Experience in CPU/ASIC design methodology and flow development, particularly in the RLS, Structural Design, APR and low power optimization domains
- Unix skills, programming skills in TCL, Perl Script and shell scripting.
- Good understanding of overall CPU/SOC design cycle and requirements.
- Ability to multi-task and flexibility to work in a global environment
- Good communication skills and have self-motivation.
- Good analytical and Problem solving skills.
- Experience in working on high frequency designs and methodologies
- Experience in leading small teams to design IPs
Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
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Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
JobType
Hybrid
