AddressJob Description
Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional Design Verification.
Qualifications
Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or school work/classes/research. Education Requirement:- Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6-8 years of industry work experience, or- Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5-7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4+ years of related work experience. Minimum Qualifications:- 6+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth know how. Solid work experience in developing SystemVerilog/UVM based testbench to verify Ethernet MAC and PHY Subsystems including SERDES and PCS Layer. Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python. Proficient in debugging complex IP designs, Ethernet PHY subsystems, High speed interfaces. Knowledge of advanced computer architecture and micro-architecture concepts. Experience with writing directed and random test cases including develop and maintain test plans, test cases. Experience with Design Verification and validation methodologies and strategies. Work with vendors and IP providers to integrate their IP into testbench Work closely with architecture, design and verification teams to ensure successful tapeout Participate in design and verification reviews, technical discussions and provide technical guidance Good communication skills and a team player. Able to work independently in a fast-paced team and environment. Desired Requirements- Deep knowledge of Ethernet/Networking protocols, Ethernet - MAC and PHY, PCS, FEC, PTP/IEEE-1588, Auto negotiation, Flow control. Familiarity with Third party Ethernet VIP usage, UNH-IOL Compliance testing is added advantage.
Inside this Business Group
The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
JobType
Hybrid
