AddressDesign Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics for bug tracking and code coverage, debug failures, and provide feedback to the design team. […]
Work closely with the design team to ensure the Company is meeting design requirements for projects. This may include review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benches. […]
Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as...
