Soc Power Management And Clock Rtl Designer Engineer

Job Details:Job Description: 

Job Description: If you are passionate about GPU for AI driven workload and working with leading graphics engineers on Intel's latest GPU/CPU architectures, then our Datacenter GFX and AI Engineering (DGAI) Team has opportunities for you. Datacenter GFX and AI Engineering (DGAI) is responsible for delivering industry-leading GPU hardware Intellectual Property (IP) blocks and system-on-chip (SoC) products for High Performance Computing (HPC). We strive to lead the industry through continuous innovation and world-class engineering. The Discrete Graphics SoC team is within DGAI and we are responsible to work with state of the art technologies and great Power Performance Area (PPA) architectures. As a member of Power Management and Clocking team, you will be working on low-power solutions for various aspects and design blocks along with SoC clocking. You will be collaborating with architects, RTL Validation, Platform and Software teams to analyze and implement low-power solutions, SoC clocking for next generation Intel GPU products for HPC. We work closely with partners across Intel and we are looking for a SoC Design Engineer to join our team.In this position you will help us with the following responsibilities:

- Participate in the development of Architecture and Microarchitecture specifications for SOC Level Clocking, Reset and/or Power Management features

- Define and implement new features in RTL at IP or SOC level

- Collaborate with cross-functional teams (FW, Validation, SD, SV, etc.) to make sure designs are delivered on time and with highest qualityClosely work with Verification team and help define testplan and debug design.Participate and drive timing convergence for high speed designs including micro-architecture optimizationsExperience with design tools and flows such as Lint, CDC/RDC, UPF/VCLP

- Behavioral traits that we are looking for:

- Good communication and collaboration skills.

- Possess strong teamwork, problem-solving and influencing skills along with abilities to work with different geographical locations

- Ability to work independently and proactively to lead technical activities

Qualifications:

Qualifications: Minimum skills and experience that will get you notice:

You must possess a minimum of Bachelor Degree in Computer Engineering, Computer Science or Electrical Engineering with 7+ years of industry experience. Or a Master with 5 + years of industry experience.

Your experience should be in the following:

- High performance digital logic designs and integration

- SOC architecture, design flows and debug skills

- Experience in SoC Power Management

- RTL design using Verilog/System VerilogStrong experience with Design of Data path Power management flows Arbitration logic , Clock Domain Crossing and State MachinesStrong knowledge of digital design involving multiple clock domains and Power Management.Knowledge of low power design, tools and methodologies. Power intent UPF specifications knowledge a plus.

- Preferred skills and experience that will make you stand out:

- Expertise with understanding of the power Management, reset, clock, and power domain challenges for large SoCs

- Experience with Design of Data path Power management flows Arbitration logic , Clock Domain Crossing and State Machines

- Knowledge of digital design involving multiple clock domains and Power Management.

- Knowledge of low power design, tools and methodologies. Power intent UPF specifications knowledge a plus.

- FE/RTL tools and design methodologies

Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:India, HyderabadBusiness group:In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.