Senior Signal Integrity And Power Integrity Engineer

Job Details:Job Description: In this role, you will be part of a world-class Silicon design enablement team of highly talented engineers working on Signal and Power Integrity who will take up significant technical role and be expert in one or more technical fields. Enable Signal and Power Integrity solutions for standard and custom designed serial / parallel I/Os. 3D and 2.5D modelling in HFSS, simulations in ADS, Cadence PowerSI, PowerDC, OptimizePI, or equivalent Ansys Tools like Redhawk, Totem, SIwave. Provides solution for Signal and Power Integrity on die, package and board which affects performance and Power of serial and parallel interfaces. Hands on Signal and Power Integrity design, frequency and time domain analysis, Simulations, System modelling, I/O modelling and measurements In this position, you will be responsible for providing Silicon, package (including 3d, 2.5d, 2d pkg technology) and platform Power and Signal integrity solutions and working closely with design teams for implementation. � Qualifications Your responsibilities will include but not be limited to: Understands different IP electrical requirements and performs comprehensive simulations and validations to generate Intel design guidelines to guide system-level signal and Power Integrity design including, but not limited to, Silicon, package, socket, boards, and voltage regulators. Performs DC, AC and transient simulation to provide noise, impedance profile of the whole power delivery path and link/electrical simulations to validate I/O performance from platform to silicon. Perform time domain analysis in HSPICE, ADS to find noise levels in I/O rails. Provides guidance, solution space on implementation with the design team ( IP, SOC, Package and board). Modelling and delivering IP SI and PI collaterals (AMI- IBIS, Die Models, ICCt, Integration guide etc..) for delivering to internal and external customer. Correlating simulations with system measurements. Deliver optimized SI and PI solution meeting the product performance Provides DC and resistance simulation to provide Rpath from the VR to the package pins, voltage drop, current density and Power loss analysis. Performs transfer impedance simulations to provide plane split and isolation guidance between interfaces on board package area. Interface with customers and in-house IP, SOC and platform teams to provide the solution to meet the SpecificationQualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. 8+ Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field. Experience in bump-out , ball map optimization Power Integrity requirements for packages Good understanding on High speed traces modeling for SI evaluation Fair knowledge on platform design simulations and validation Teamwork / flexibility / ability to thrive in a dynamic environment are very importantJob Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.