Senior Rtl Design Engineers (5 Years Experience)  

"Expert in Verilog, digital design, FPGA design process and synthesis
Participate in the definition of the design and system architecture for complex FPGA solutions
Develop VHDL / Verilog code for various system blocks
Participate in size / timing optimization of complete FPGA design
Place & route flows, pinning, timing optimization for Xilinx and / or Altera
Tool: , Xilinx Vivado, Altera Quartus.
Continuously improving test and simulation environment to assure FPGA
Good hardware debugging capability using industry standard test equipment like Protocol
Generator/ILA/Scope/Signal Analyzer/chip scope...