AddressJob Description
Responsibilities include but not limited to: Tops-down floor planning of an SOC or a Full Chip IP in collaboration based on Package, Bump and technology constraints. Estimate of Die area. Collaboration with IP and Package owners to finalize IP/sub system Placement. Definition of Bump-map in collaboration with IP Owners and delivering Validated Die file to Packaging and other stakeholders. Influencing Physical Partition of the Sub-Blocks, Shape and Pin Planning, Power Grid Planning and channel planning and delivering Tops-down constraints to partition owners for place and route. Definition Chip integration contour including PDK, Tools, IP and Bump versions. Driving for Layout Verification Convergence for DRC, LVS, Density and Power Delivery.
Qualifications
A Masters of Engineering degree in Electrical/ Electronic Engineering/ VLSI Engineering and minimum 10 plus plus years of hands-on experience OR Bachelor of Science degree in Electrical/Computer Engineering with 12+ yrs of relevant experience Experienced Floor planning at Chip level/Subsystem Level in high performance computing space Experienced Floor planning at Chip level/Subsystem Level at least minimum of 2 at the chip level Must have experience on 5nm or below Industry Process Must be experienced in SNPS/Cadence floor planning tools Scripting Skills in Python, Perl and TCL needed. Must be a strong communicator, excellent in verbal/written communication.
Inside this Business Group
The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
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Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
JobType
Hybrid
