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Job Description:
The Standard Cell Team is part of the Design Enablement/Advanced Design Group in Technology Development.
Its main charter is in design, development, QA, and delivery of testchip/benchmarking Standard Cell libraries using leading process technologies for use in the design of Intel's next-generation SoCs and microprocessors.
Responsibilities may include but not limited to:
Characterization of Standard Cell library, view generation and library release
Generate all required views (NDM,LEF,FRAM, ATPG,UDFM etc)
Strive to ensure the quality of releases, drive implementing QA checks to improve robustness of the delivery (consistency and completeness of the views, usability in the EDA tools)
Work with vendors to get the PVT char setup and drive generation of custom PVTs are required by the methodology/design team (Silicon Smart)
Establish best-in-class QA methodology for maximum coverage.
Understand, analyze, and drive improvements to existing methodologies
Automation of repeatable tasks for productivity improvements.
Documentation of workflows, issues, debugs, lessons learned from the projects, and presentations to the team.
Qualifications
Minimum Qualifications: You must possess a minimum of Master's degree with VLSI specialization. Desired Skills and Experience: Experience in layout design and verification of Standard Cell circuits. Strong CMOS circuit design basics, MOSFET device physics, intel PDK's Understanding of characterization methodologies for timing, power, constraints and familiarity with characterization challenges of special cells like synchronizers, multibit cells, etc. Understanding of static timing analysis, library benchmarking (cell level and design level) requirements. Knowledge of the complete characterization flows, library validation and timing/ power characterization methodologies for Standard Cells. Familiarity with Simulators, liberty syntax requirements, CCS, statistical characterization, Verilog models, UDFM , STA and power analysis tools Understanding issues related to advanced nanometer technologies like EM/ IR, SI, LOD and proximity - effects Scripting skills with perl, shell, python or tcl. Good understanding of advanced MOSFET process and FinFET process technologies and their benefits and challenges for circuit design and layout design.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
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Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
JobType
Hybrid
